Reference is now made to FIG. 1 which illustrates a prior art virtual ground memory array. The memory array typically comprises columns of bit lines 10 between which are columns of memory cells 12. The bit lines 10 are typically switchably connected, via EQ transintors 13, to a capacitive node known as the "common node bit line" (CNBL line) which, in turn, is connected to an amplifier or pull-up transistor 14. Each bit line 10 is additionally connected to a small keeper transistor 16 and to a Y-decoder 18. The transistors 13, 14 and 16 are n-channel transistors.
EQ transistors 13 are each controlled by an EQ line and the pull-up transistor 14 and the keeper transistors 16 are controlled by a blvref line carrying a generally steady reference voltage. For a 2 V CNBL voltage and a 0.8 V threshold of the n-channel transistors 14 and 16, the blvref voltage is approximately 3.2 V.
Prior to accessing a memory cell 12, the EO transistors 13 connect the bit lines 10 to the CNBL line and enable the memory array to become pre-charged to a pre-charge voltage level, typically of 2 V.
Prior to accessing a memory cell 12, the bit lines 10 are disconnected from the CNBL line. During access of a memory cell 12, one of its neighboring bit lines 10 (the one which becomes the source line) is grounded and the voltage on the other neighboring bit line 10 (which becomes the drain line) is connected through the Y-decoder 18 to a sense amplifier (not shown) which senses the state of the data stored in accessed memory, cell 12.
During accessing, the keeper transistors 16 maintain the voltage levels of the other bit lines 10 at or dose to the pre-charge voltage level which, for the above example, is 2 V. The keeper transistor 16 on the bit line of the accessed memory cell 12 also fights the activity of the accessed memory cell. However, as long as the read signal that can be detected on the drain line is small, say of 100 mV, the drain-to-source voltage Vds on keeper transistor 16 is small. Since, by design, the size W/L of the keeper transistors 16 is small, the action of the keeper transistor 16 on the accessed bit line practically does not affecting the memory cell read.
Once the data from the memory cell 12 has been read, the EQ transistors 13 can reconnect the entirety of bit lines 10 to the CNBL line, thereby enabling the memory array to redistribute its charge. The charge redistribution pre-charges the used bit lines 10 but reduces the charge level of the CNBL line. In response, the pull-up transistor 14 pulls the CNBL line to the pre-charge voltage level. Since the keeper transistors 16 kept the unused bit lines 10 at close to the pre-charge voltage level, the change in the voltage of the CNBL line due to charge redistribution is on the order of 200 mV which is relatively small.
The memory array typically has two modes of operation, an active mode in which the memory cells 12 are accessed every access time t.sub.aa nanoseconds and a standby mode during which no activity occurs and therefore, there is no current in the memory array. A typical value for t.sub.aa in non-volatile memory products is in the range of 25-200 nanoseconds.
During the active mode, the charge redistribution and corresponding pull-up activity provides an average current for transistor 14 on the order of milliamperes. During the standby mode, the only current that transistor 14 must replenish is its junction leakage current which is less then a picoampere.
FIG. 2, to which reference is now made, is a log-linear chart which illustrates an exemplary current-voltage graph 23 for the pull-up transistor 14, where, for example, the pull-up transistor 14 has a size of 2000/1.1 .mu.m. It is noted that the voltage on the CNBL line is the source voltage of transistor 14. The V.sub.CNBL level is determined by the voltage level of blvref, which for curve 23 is 3.2 V, and the amount of current flowing out of the CNBL node.
For V.sub.CNBL from 0 to 1.4 V, pull-up transistor 14 is in saturation. For V.sub.CNBL at approximately 0 V, transistor 14 conducts several tens of milliamperes. For V.sub.CNBL at 1.6 V, transistor 14 conducts a few milliamperes (point 20 on graph 23). From 1.6 V to 1.8 V (from point 20 to point 22), transistor 14 is in transition to a subthreshold state. In the active state, (i.e. voltages greater then 1.8 V), as V.sub.CNBL increases, the current drops by about one order of magnitude for every 90 to 100 mV.
For a constant blvref, which is generally available, a decrease in the current from 100 .mu.A to 10 .mu.A will increase the CNBL voltage level V.sub.CNBL by 90 mV from 1.8 V to 1.89 V and a current increase to 1 mA will reduce the CNBL voltage level V.sub.CNBL 150 mV from 1.8 V to 1.65 V.
It is noted that, if the CNBL current is constant, which is a rare situation, the voltage level V.sub.CNBL changes in one-to-one correlation with the steady blvref voltage. For example, a blvref of 4.2 V will produce a CNBL voltage level V.sub.CNBL of 2.8 V and a CNBL current of 100-200 .mu.A.
When the memory array is active, the transistor 14 typically operates with a variable current level between 1 mA and 100 s of microamperes. Thus, its maximum voltage level is approximately 1.6 V, which is indicated by point 20.
When the memory array is in standby mode, the current is typically on the order of picoamperes and the operating point is near a point 24. As can be seen when contrasting points 20 and 24, the reduction of current, during standby, by eight orders of magnitude increases the CNBL voltage level V.sub.CNBL to about 2.5 V. This is problematic.
Furthermore, the keeper transistors 16 also follow a similar current-voltage graph, except that, since they are smaller, the graph, labeled 25 in FIG. 2, begins at a lower level. However, its slope is mode, identical to that of graph 23. If the memory array is in standby during which the EQ transistors 13 are inactive, the voltage levels of the bit lines 10 are defined by the leakage current of the keeper transistors 16. For example, If the keepers 16 are part of a 1 Mbit array with 1000 bit lines and are 1000 times smaller them transistor 14, their leakage current (during standby) is 1000 times smaller then that of the transistor 14 and therefore, their standby operating point, labeled 27, has the same voltage as the standby operating point 24 of the transistor 14. In other words, during standby, the keepers 16 provide the bit lines 10 with a voltage level of about 2.5 V.
When reading a memory cell 12, its neighboring bit lines 10 are typically quickly brought to their voltage levels for reading by the Y-decoder 18. The data in the memory cell 12 is determined by comparing the output of the reading bit line to that of a reference bit line attached to a memory cell whose data value is known.
Normally, this poses no problem. However, if the memory array has been in standby mode, the keeper transistors 16 have raised the voltages on all the bit lines 10. Prior to reading a memory cell, the memory array is equalized; however, when the voltages are too high, the equalization typically does not return the voltages to their pre-standby values. A bit line which previously was a source line (i.e. at ground) will start, in this case, from a non-equalized state while the reference bit line against which it may be read will be at the pre-charged level. To read such a bit line will take longer to generate the correct signal then is allotted and an incorrect reading will be produced. The result is a failed memory array.
The voltage difference between the reference bit line and the reading bit line is added to the voltage that the memory cell generates. Since it takes longer to generate a larger signal and the time allotted for producing a signal is fixed, the signal which is produced in this case will be lower then it should be. How serious this problem is depends on how much time the memory array spends in the standby mode and the voltage level it comes to as a result.
Another example of the problem of varying CNBL currents which leads to a problem is the reading of a "1" after reading a "0". When a "1" is read from a memory cell, about 100 .mu.A of current per memory cell is pulled from the active bit line 10 and therefore, during pre-charge, the pull-up transistor 14 requires current in the order of milliamperes in order to equalize the memory array. If a "0" is read, no current is pulled from the active bit line 10. Normally this is of no consequence. However, if the memory cells 12 of a single bit line 10 are read consecutively and they all have "0"s stored therein, only the junction leakage current is pulled from the active bit line 10 and therefore, its voltage level increases, as in the standby mode, towards keeper operating point 27. This causes incorrect data reading problems such as described hereinabove for the standby mode, It is therefore desired to stabilize the CNBL voltage level V.sub.CNBL and the voltage of the bit lines connected to it, between the active and standby modes to a range much less then the 0.5-0.7 V of the prior art circuits.
Prior art memory arrays solve the active vs. standby problem by providing different voltage levels for the blvref signal, one for each mode thereby, providing transistor 14 with two operating regions. This solution is optimized for one operating temperature and for one set of process conditions. If the temperature or process condition changes, the two levels for the blvref signal also change. Hence, this solution still maintains a wide range of CNBL levels and does not solve the wide operating range problem.